Field of the Invention
The invention relates in general to a de-interleaver and a de-interleaving method, and more particularly to a convolutional de-interleaver and a convolutional de-interleaving method.
Description of the Related Art
In communication transmission technologies (e.g., the orthogonal frequency division multiplexing (OFDM) wireless transmission technology), in order to reinforce the resistivity of signals against interference, a time interleaving process is applied at a transmitting end, and a time de-interleaving process is applied at a receiving end. FIG. 1 shows a structure of a time interleaving process. The structure 100 includes K interleaving processing units 110, each including nc input ends and nc output ends that sequentially receive and output signals according to signal sampling clocks. As shown in FIG. 2, each of the interleaving processing units 110 includes nc paths for performing an interleaving process on signals.
The above interleaving processing unit 110 may implement a convolutional interleaving process. Referring to FIG. 3 showing the interleaving processing unit 110 according to an embodiment, between the 1st input end and the 1st output end is a delay ((nc−1)D) of nc−1 unit, between the 2nd input end and the 2nd output end is a delay ((nc−2)D) of nc−2 unit, between the (nc−1)th input end the (nc−1)th output end is a delay (D) of one unit, and between ncth input end and the ncth output end is no delay (bypass). The delay in each unit according to design requirements may be I signal periods or signal sampling clocks, where I is a positive integer. After processing the signals by the above convolutional interleaving process, the signal receiving end includes a convolutional de-interleaving structure for performing a de-interleaving process. The convolutional de-interleaving structure includes K de-interleaving processing units, each similarly sequentially receiving and outputting signals according to signal sampling clocks, and correspondingly includes a delay arrangement reverse to that of the interleaving processing units 110. As shown in FIG. 4, between the 1st input end and the 1st output end of the de-interleaving processing unit 410 is no delay (bypass), between the 2nd input end and the 2nd output end is a delay (D) of one unit, between the (nc−1)th input end the (nc−1)th output end is a delay ((nc−2)D) of nc−2 unit, and between the ncth input end and the ncth output end is a delay ((nc−1)D) of nc−1 unit.
The delay of various units in the receiving end may be realized through delay buffers. In one conventional solution, the function of delaying buffers is achieved by a static random access memory (SRAM). Although the SRAM has a fast access speed, it disfavors cost effects as being quite costly. In another conventional solution, a shared system memory is utilized to realize the function of delaying buffers. A system memory, usually a synchronous dynamic random access memory (SDRAM), has a lower cost and thus saves hardware costs. However, in this conventional solution, data is sequentially written into the SDRAM according to a receiving sequence of the data (i.e., memory addresses written at earlier time points are also sooner over-written). It should be noted that, due to the convolutional interleaving process at the transmitting end, the receiving sequence is not arranged according to the continuity of data. Thus, to restore the continuity of data during the convolutional de-interleaving process, the above conventional solution is required to read data from memory addresses at different rows. That is to say, because of the structure and access method of the SDRAM, when multiple sets of data to be de-interleaved is stored in different row regions in the SDRAM, a pre-charge operation needs to be performed after completing the first read operation to shut down the row address region corresponding to the first read operation, and then a row active operation is performed to open the row address region corresponding to the second read operation. As such, when multiple sets of data is interleavingly stored in different row regions, the additional pre-charge and row active operations inevitably consume tremendous access time due to the constant row access changes. In conclusion, such conventional solution not only needs a longer convolutional de-interleaving processing time, but also affects memory bandwidths of other circuits accessing the system memory.